The present invention relates to a thin film transistor element array disposed on an insulating substrate, and more specifically, it relates to the thin film transistor element array having a wire electrode suitable for being used for an active matrix type liquid crystal display.
Recently, the demand of the liquid crystal display has risen. More specifically, since the active matrix type liquid crystal display wherein the thin film transistor is disposed as a switch of each pixel on one glass substrate has a high quality image, more and more demand is growing. In order that such a liquid crystal display may be developed henceforth, the reduction of cost is a critical problem. A manufacturing process is required to be simplified. In an example of the prior art relating to the simplification of a photolithography process, there is disclosed the active matrix type liquid crystal display by the use of the thin film transistor element whose structure can be formed by means of two-time photolithography process.
FIGS. 1A, 1B and 1C are a plan view and a cross sectional view showing the structure of the thin film transistor, a first conventional example used for the active matrix type liquid crystal display, which can be manufactured by means of two-time photolithography process (Japanese Patent National Publication (Kohyo) No. 501562/1984). In the structure according to the conventional example, a portion 1--1 functions as the thin film transistor. An ITO (Indium Tin Oxide) film 21 functions as a signal wire. A metal film 6 functions as a control wire. An ITO film 22 functions as a pixel electrode. Next, the manufacturing process according to the conventional example will be described. A laminated film of the ITO film and an n.sup.+ amorphous silicon film are sequentially formed on a transmittable insulating substrate 1. After the photolithography process, a pattern is formed. Next, the laminated film of an amorphous silicon semiconductor film 4, an insulating film 5 and the metal film 6 is formed. After the photolithography process, the pattern is formed. At this time, an n.sup.+ amorphous silicon film 3 on the ITO films 21, 22 is also removed. Although six to seven mask patterns are normally necessary, in case of the conventional example, the thin film transistor element array is formed by two-time photolithography process.
As proposed by a second conventional example (Japanese Patent National Publication (Kohyo) No. 500745/1987), when disconnection arises on the ITO film 21 in the first conventional example, the n.sup.+ amorphous silicon film 3 is left on one part of the ITO film 21 for a reinforcement. FIGS. 2A, 2B and 2C are a plan view and a cross sectional view to describe the second conventional example. The manufacturing process of the second conventional example is the same as the first conventional example up to the formation of metal films 61 and 62. When the pattern is formed by means of the photolithography process, the laminated film pattern of the n.sup.+ amorphous silicon film 3, the amorphous silicon semiconductor film 4, the insulating film 5 and the metal film 62 is left on one part of the ITO film 21, isolating from the thin film transistor element comprising the laminated film pattern of the amorphous silicon semiconductor film 4, the insulating film 5 and the metal film 61. Accordingly, in the second conventional example, as shown in FIG. 2C, a cross sectional view taken on line 3--3 of FIG. 1A, the structure of a signal wire portion is the laminated structure of the ITO film 21, the n.sup.+ amorphous silicon film 3, the amorphous silicon semiconductor film 4, the insulating film 5 and the metal film 61. Therefore, even if disconnection arises on the ITO film 21, an electrical connection is held by the n.sup.+ amorphous silicon film 3.
FIGS. 3A, 3B and 3C show the structure of a third conventional example which is intended to reduce a resistance of a drain wire. In the structure, a first metal film 10 is disposed on the ITO film 21, whereby the resistance of the drain wire is reduced. The manufacturing method of the conventional example is the same as the first conventional example up to the formation of the pattern of the ITO films 21, 22 and the n.sup.+ amorphous silicon film 3. Next, the pattern of the first metal film 10 is formed. Thenceforth, the method is the same as the first conventional example from the formation of the amorphous silicon semiconductor film 4. Accordingly, the resistance of the drain wire can be reduced by means of three-time photolithography process.
According to the first and second conventional examples, the resistance of the signal wire is very high. Accordingly, in case that the examples are applied to a liquid crystal display device having a large screen, there is such a problem that correct images cannot be carried out due to a drain signal delay at a position separated from a signal input terminal. The reason is as follows. According to the first conventional example, the signal wire comprises a single layer of the ITO film 21 having a high resistivity. According to the second conventional example, it is the laminated film of the ITO film 21 and the n.sup.+ amorphous silicon film 3 that electrically contributes among the laminated films constituting the signal wire. Accordingly, in both the example, the signal wire has the high resistivity.
Another problem of the first, second third conventional examples is as follows. Since a leakage current flows between the pixel electrode and an adjacent drain electrode wire, a voltage applied to the pixel is dropped, whereby the display of the liquid crystal display is not normal. The reason is that the laminated structure of the amorphous silicon semiconductor film 4, the insulating film 5 and the metal portion 61 is all over the area of a gate electrode wire whereby a parasitic transistor exists between the pixel electrode and the adjacent drain electrode wire.
Moreover, there is a further problem of the first to third conventional examples that an auxiliary capacitance for restraining a change in an electric potential of the pixel electrode cannot be formed. The reason is as follows. In order to form the auxiliary capacitance between the pixel electrode and the one line previous gate electrode, the pixel electrode, that is, the ITO film 22 is overlapped with the one line previous gate electrode wire. In this case, the leakage current flows between the pixel electrode and the drain electrode wire via the parasitic transistor described above, whereby it is difficult to normally hold a pixel potential.